1. Field of the Invention:
The present invention relates to a method and apparatus for transferring data among various components of a computer system. More particularly, the present invention relates to an improved computer bus with virtual memory capabilities.
2. Art Background:
In a typical computer system, a central processing unit (CPU) reads from, and writes data to, peripheral devices and other components which comprise the data processing system. This communication between devices is frequently accomplished by means of a bus which interconnects all of the components of the computer system. The speed at which the bus transfers data directly limits the overall speed of the computer system. Common constraints on the speed of data transfer between components coupled to the bus are protocol or "handshake" restrictions. These require a predetermined sequence of events to occur within specified time limits prior to an actual exchange of data between the devices coupled to the bus. It is therefore desirable to have a high speed and high bandwidth bus which operates quickly to minimize the computing time required for a particular task. The protocol utilized by the bus should be designed to be as efficient as possible and minimize the time required for data transfer.
In addition, many systems employ virtual memory schemes to increase the capability of the data processing system. As is well known, virtual memory techniques permit a CPU to address more memory then there is physically present in the computer system's main memory. When the CPU needs to read or write data in main memory, it generates a virtual address for the data. This virtual address is translated into a physical address by a memory management unit (MMU). The physical address is then applied to the main memory to read or write data at that address. Since the time required for the CPU to access main memory is typically much less than the access time for a peripheral device (such as an external disk drive), overall speed of program execution is increased.
The MMU accepts a virtual address generated by the CPU and translates it into a corresponding physical address located in main memory. If the translation data is not currently stored in the MMU, then the MMU transfers the proper translation data into its memory from main memory or another peripheral device. MMU's also provide capabilities such as multiple address spaces for separate processes, sharing of memory between processors, and the protection of desired memory locations by permitting only certain operations such as read, write, or execute to such areas. A variety of virtual memory systems are known in the field of computer systems, and are commonplace in state-of-the-art computing equipment. One such type of memory management unit is described in U.S. Pat. No. 4,550,368.
Another limitation on a computer bus is the size of the bus itself. Essentially, a bus is a collection of wires connecting the various components of a computer system. In addition to address lines and data lines, the bus will typically contain clock signal lines, power lines, and other control signal lines. As a general rule, the speed of the bus can be increased simply by adding more lines to the bus. This allows the bus to carry more data at a given time. However, as the number of lines increases, so does the cost of the bus. It is therefore desirable to have a bus which operates as quickly as possible while also maintaining a bus of economical size.